1. Field of the Invention
The present invention relates to down conversion filters.
2. Description of the Related Art
FIG. 1A depicts a conventional down conversion filter with switched-capacitor circuits. FIG. 1B illustrates the waveforms of signals clk1-clkN, which control the switches of FIG. 1A.
Referring to FIG. 1B, the signals clk1-clkN are periodic signals dependent on the clock pulse width, having non-overlapping and successive duty periods. Each duty period (having a length of 1/fS) lasts one clock phase. The signals clk1-clkN-2 provide sampling phases that alternatively sample the input signal (at the input terminal IN) in the sampling capacitors C1-CN-2. The signal clkN-1 provides a charge-summing phase that transfers charges from the sampling capacitors C1-CN-2 to the charge-summing capacitor CS. The signal clkN provides a discharge phase that resets the sampling capacitors C1-CN-2 for a good signal-to-noise ratio.
The down conversion filter of FIG. 1A sums out the successively sampled signals every N clock phases. Thus, each output cycle includes N clock phases, and the tap length of the circuit is N. During each output cycle (including N clock phases), one clock phase is reserved for the charge-summing phase, one clock phase is reserved for the discharge phase, and only the rest (N−2) clock phases are reserved for the sampling phases. Because the number of the sampling capacitors is dependent on the number of the available sampling phases and the performance of the down conversion filter is controllable by designing the values of the sampling capacitors, the reserved discharge phase limits the flexibility of the controllable coefficients of the system.